1. Field of Invention
The present invention relates to a method of fabricating memory. More particularly, the present invention relates to a method of increasing the data retention capacity of a silicon nitride read-only-memory cell.
2. Description of Related Art
Flash memory is a type of programmable/erasable non-volatile memory. Aside from power down data retention capacity, flash memory also has in-circuit electrical programming and erasing capability. Thus, flash memory is deployed as a non-volatile memory device inside most personal computers and electronic equipment.
Flash memory can be classified into two major types, including doped polysilicon floating gate read-only-memory and silicon nitride read-only-memory with the silicon nitride layer serving as a charge-trapping layer. The electrons for injecting into the silicon nitride charge trapping layer of the silicon nitride read-only-memory is concentrated within a localized region.
For a silicon nitride read-only-memory, data retention period in excess of ten years is often demanded besides the normal reliability requirements in all memory devices. Furthermore, the silicon nitride read-only-memory must operate normally after numerous programming and erasing operations. To meet such stringent conditions, the silicon nitride read-only-memory must undergo a cell retention check during a reliability test. In general, the cell retention check is carried out during a wafer sort test. The check includes heating the finished wafer product to a temperature of about 250° C. and maintaining at this temperature for a 24-hour period. During the check, a high voltage is applied to the memory to conduct data programming.
In the process of fabricating the silicon nitride read-only-memory, the two outermost word lines located on each side of the memory cell array are vulnerable to various types of in process damages, ultimately damaging the tunnel oxide layer. Moreover, some of the steps may require a plasma treatment leading to some holes trapped within the damaged tunnel oxide layer. In a convention fabrication process, the silicon nitride read-only-memory wafers are sorted after conducting a wafer acceptance test (WAT) and a quality control visual inspection. If the wafer is damaged so that the tunnel oxide layer contains trapped holes, these holes may induce the charges within the charge-trapping layer to leak into the substrate through the tunnel oxide layer during a cell retention check. Ultimately, there is a loss of charges leading to a lowering of memory retention capacity and threshold voltage.